I couldn't prevent unaligned load-store instructions

[omerkarslioglu]

Hi,

I turn off all parameters related with unaligned load-store instruction in riscv-dv (in yaml files, and systemverilog config file for the target).

But I am still getting unaligned store double instruction:

core   0: 0x000000008000a5a2 (0x00223023) sd      sp, 0(tp)
core   0: exception trap_store_address_misaligned, epc 0x000000008000a5a2
core   0:           tval 0x000000008000b0fc

Is there anything else that I should do?

Thanks,
Omer