pyproject.toml

[build-system]
requires = ['setuptools >= 61.0']
build-backend = 'setuptools.build_meta'

[project]
name = 'fsyn'
version = '0.1.0'
dependencies = ['fabric', 'Flask', 'requests', 'wal-lang']
requires-python = '>=3.7'
description = 'Reduce netlists using formal tools'
readme = 'README.md'
license = {text = "MIT License"}
keywords= ['verilog', 'development', 'hardware', 'rtl', 'simulation', 'FPGA']
classifiers=[
        'Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)',
        'Development Status :: 4 - Beta',
        'Intended Audience :: Science/Research',
        'Intended Audience :: Developers',
        'License :: OSI Approved :: MIT License',
        'Programming Language :: Python :: 3 :: Only',
        'Operating System :: OS Independent'
]

[project.scripts]
fsyn = 'fsyn.main:run'
fsyn_local = 'fsyn.local:run'
fsyn_local_ec = 'fsyn.local_ec:run'
fsyn_client = 'fsyn.client:run'
fsyn_api = 'fsyn.api:run'