VLSI System Design (VSD) - Research Program

This repository is a record of all the task being performed in 10 weeks VSD-Research Program.

Content

• WEEK-1
• WEEK-2
• WEEK-3
• WEEK-4
• WEEK-5

WEEK-1

To install xschem:

$  git clone https://github.com/StefanSchippers/xschem.git xschem_git
$	./configure
$  make
$  sudo make install

To install magic:

$  git clone git://opencircuitdesign.com/magic
$  cd magic
$	 ./configure
$  make
$  sudo make install

To install Sky130 pdk:

$  git clone git://opencircuitdesign.com/open_pdks
$  open_pdks
$	./configure --enable-sky130-pdk
$  make
$  sudo make install

To install ALIGN:

export CC=/usr/bin/gcc
export CXX=/usr/bin/g++
git clone https://github.com/ALIGN-analoglayout/ALIGN-public
cd ALIGN-public

#Create a Python virtualenv
python -m venv general
source general/bin/activate
python -m pip install pip --upgrade

# Install ALIGN as a USER
pip install -v .

# Install ALIGN as a DEVELOPER
pip install -e .

pip install setuptools wheel pybind11 scikit-build cmake ninja
pip install -v -e .[test] --no-build-isolation
pip install -v --no-build-isolation -e . --no-deps --install-option='-DBUILD_TESTING=ON'

To make ALIGN portable to sky130 pdk:

$git clone https://github.com/ALIGN-analoglayout/ALIGN-pdk-sky130

To check if the installation is correct:

mkdir inverter
$ cd inverter
$ mkdir mag
$ mkdir netgen
$ mkdir xschem
$ cd xschem
$ cp /usr/local/share/pdk/sky130A/libs.tech/xschem/xschemrc .
$ cp /usr/local/share/pdk/sky130A/libs.tech/ngspice/spinit .spiceinit
$ cd ../mag
$ cp /usr/local/share/pdk/sky130A/libs.tech/magic/sky130A.magicrc .magicrc
$ cd ../netgen
$ cp /usr/local/share/pdk/sky130A/libs.tech/netgen//sky130A_setup.tcl .

waveform	Values

The output reaches 50% in 389.25ns.

waveform	Values

The output reaches 50% in 390.38ns.

waveform	Values

The output reaches 50% in 411.97ns.

Week-1 Conclusion

Thus, the difference in delay observed when comparing pre-layout simulation with post layout simulation using magic is 1.13ns. And when compared to post layout simulation using ALIGN is 22.72ns. The delay is caused due to parasitics in the circuit.

Week-2

Prelayout and Postlayout simulation of a function Fn = [(B+D).(A+C)+E.F]'

I first create schemetic on Xschem and made the necessary connections. A pulse input is provided to each input A, B, C, D, E, F and the output is taken from port Y.

Then the schematic is simulated using ngspice. I obtained the following waveform:

Now, I performed post-layout simulation of the function using Magic. First, the spice file for the function is imported in magic and all the parasitic in the crcuit are extracted which is shown by the screenshot below:

New spice file is generated by magic. In the new spice file, I added input pulse and simulate it using ngspice. The following waveform is obtained.

The waveform is similar to that of pre-layout simulation. However, I observe small delay in the waveform that might be caused due to parasitics in the layout.

Now, I perform post-layout simulation using ALIGN. Here, I first ran ALIGN on the spice file generated by xschem and generated .gds and .lef file. These files can be viewed using klayout. In magic, I read the .gds file. Some DRC(Design Rule Check) errors were observed. I first removed all the DRC errors and extracted spice netlist as shown in the screenshot below.

Then, a new spice file is generated. I again provided the input pulse and simulated the spice file using ngspice. The following waveform is obtained.

Week-2 Conclusion

In conclusion, the waveform generated while performing pre-layout simulation and post-layout simulation are not exactly the same. In post-layout simulation, parasitic capacitence and resistance are also considered whereas in pre-layout simulation, parasitics are not considered and are connected using ideal wires which is not actually the case in real.

Post-layout simulation using magic and ALIGN are also not exactly the same. ALIGN have lower parasitics effect than Magic. Thus, we observe more delay when performing post-layout simulation using Magic than ALIGN.

Week-3

OpenFASOC

OpenFASOC is Fully Open-Source Autonomous SoC Synthesis using Customizable Cell-Based Synthesizable Analog Circuits. In OpenFASOC, we use other open-source tools such as Yosys, OpenROAD, Klayout, Magic and Ngspice. Thus, we also need to install all these tools.

To install OpenFASOC:

git clone https://github.com/idea-fasoc/openfasoc
cd openfasoc
sudo ./dependencies.sh

Installing Yosys

The packages necessary for Yosys are installed as follows:

sudo apt install -y clang bison flex \
    libreadline-dev gawk tcl-dev libffi-dev git \
    graphviz xdot pkg-config python3 libboost-system-dev \
    libboost-python-dev libboost-filesystem-dev zlib1g-dev

To install Yosys:

git clone https://github.com/YosysHQ/yosys.git
cd yosys
make
sudo make instal

Installing OpenROAD

The packages necessary for Yosys are installed as follows:

sudo apt install -y cmake qtbase5-dev qtchooser qt5-qmake qtbase5-dev-tools \
    libmng2 qt5-image-formats-plugins tcl-tclreadline \
    swig libboost-all-dev libeigen3-dev libspdlog-dev

To install OpenROAD:

cd
git clone --recursive https://github.com/The-OpenROAD-Project/OpenROAD.git
cd OpenROAD
./etc/DependencyInstaller.sh
cd
git clone --recursive https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts
cd OpenROAD-flow-scripts
./build_openroad.sh –local
export OPENROAD=~/OpenROAD-flow-scripts/tools/OpenROAD
export PATH=~/OpenROAD-flow-scripts/tools/install/OpenROAD/bin:~/OpenROAD-flow-scripts/tools/install/yosys/bin:~/OpenROAD-flow-scripts/tools/install/LSOracle/bin:$PATH

The installation took about an hour.

After installation, I ran the OpenROAD flow on a design (ibex) using sky130hd pdk to test if it is working correctly. The following screenshot shows the flow.

The screenshot below shows the layout of the design (ibex) after complete OpenROAD flow. The flow took my system almost an hour.

OpenFASOC : Temperature Sensor Generator

Here, we run a test design which is a Temperature Sensor Generator (temp-sense-gen) to get an overview of the operating process of OpenFASOC. For temperature sensor generator, the physical implementation of the analog blocks in the circuit is done using two manually designed standard cells, they are

1. HEADER cell, containing the transistors in subthreshold operation
2. SLC cell, containing the Split-Control Level Converter We should be aware that the gds and lef files for HEADER andSLC are pre-created before the start of the Generator flow.

The HEADER.gds is shown below: And, the SLC.gds is shown below: These files are present in 'openfasoc/openfasoc/generators/temp-sense-gen/blocks/sky130hd/gds'

Verilog Generation

To run verilog generation, in temp-sense-gen directory type

make sky130hd_temp_verilog

You may encounter error if you have not set PDK_ROOT.

The test.json file is an input for verilog generation.

After successfully installing OpenFASCO, change the directory to 'temp-sense-gen' directory and run the following command:

make sky130hd_temp_verilog

This creates counter.v, TEMP_ANALOG_hv.nl.v, TEP_ANALOG_lv.nl.v files in src folder.

OpenROAD Flow

The OpenROAD flow requires the generated verilog files and also 'config.mk' file. This file is present in tempsense directory. To run the OpenROAD flow

make sky130hd_temp

This should be kept in mind that this command performs full flow from verilog generation to final GDSII. The results are obtained in '/openfasoc/openfasoc/generators/temp-sense-gen/flow/results/sky130hd/temperature' directory.

The final layout of temperature sensor generator is shown below:

Week-4

Ring Oscillator Circuit

A Ring-oscillator circuit generates clock like pulses without any external input. These are usually built using odd number of NOT gates. The output of the last inverter is fedback as the input and thus the output oscillates between tow voltage level.

Pre-layout simulation

Post-layout simulation using MAGIC

Post-layout simulation using ALIGN

GDS	LEF

Week-5

1-bit ADC (Analog to Digital Converter)

A simple op-amp is used as a comparator to achieve the functionality of a 1-bit ADC. ADC are used to convert the analog signal to digital signal. The schematic of the design is shown by the screenshot below.

working

We supply a reference voltage (Vref) and a pulse as input to the circuit. If the input pulse goes above the reference voltage then the output is high '1' and if the pulse goes below the reference voltage then the output is low '0'.

We then simulate the schematic using a sine wave with frequency of 50MHz, the following waveform is obtained which shows input voltage, reference voltage and the output voltage.

Post-layout simulation using ALIGN

ALIGN takes spice netlist file as input to generate the layout. After successful ALIGN run, The following gds and lef file are obtained.

GDS	LEF

Then we generate the post-layout netlist using magic. The generated netlist is then edited to provide input voltages. The following waveform is obtained after simulation which seems incorrect. Thus, it is necessary to re re-run the flow and repeat the process.

OpenFASOC

The auxiliary cells for ring-oscillator and 1-bit ADC is obtained from the previous ALIGN flow. In addition to these auxiliary cells, we also need to provide dummy verilog files that defines the connection between the components.

Now, we connect the Ring oscillator and the ADC together as shwn in the schematic below and verify that the combination gives correct output. For this, symbols for both Ring oscillator and the ADC are created and connected. The simulation source and the library file for typical corner are also mentioned.

After simulaition using NGspice, the following waveform is obtained. Note: It is necessary to adjust the frequency of the Ring oscillator to get the correct output as the ADC cannot work properly in high frequency.

Verilog file for asynchronous up/down counter

module analog_async_up_down(
    input vref_i,
    output adc_o
);

wire osc_o;

ring_osc ring_osc_0(
    .out(osc_o)
);

adc adc_0(
    .vin(osc_o),
    .vref(vref_i)
    .out(adc_o)
);

endmodule

Verilog file for Ring oscillator

module adc(
    input vin,
    input vref,

    output out
);

endmodule

Verilog file for 1-bit Analog to Digital converter

module ring_osc(
    output clk_o
);

endmodule