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add lane data width #1013

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Merged
merged 13 commits into from
Apr 22, 2025
Merged

add lane data width #1013

merged 13 commits into from
Apr 22, 2025

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qinjun-li
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@qinjun-li qinjun-li force-pushed the lane-data-width branch 5 times, most recently from 4e5ced6 to 3f4ee44 Compare April 3, 2025 07:07
@qinjun-li qinjun-li marked this pull request as draft April 7, 2025 03:56
@qinjun-li qinjun-li marked this pull request as ready for review April 8, 2025 08:26
@qinjun-li qinjun-li force-pushed the lane-data-width branch 4 times, most recently from 36a642b to 1819167 Compare April 15, 2025 05:11
@Clo91eaf Clo91eaf force-pushed the lane-data-width branch 2 times, most recently from a78d6a9 to dffca18 Compare April 16, 2025 08:00
@qinjun-li qinjun-li force-pushed the lane-data-width branch 15 times, most recently from 954199c to 7392a42 Compare April 20, 2025 06:42
@qinjun-li qinjun-li force-pushed the lane-data-width branch 5 times, most recently from 59327a4 to 37ab2ec Compare April 21, 2025 09:39
Clo91eaf and others added 11 commits April 22, 2025 12:08
Signed-off-by: Clo91eaf <Clo91eaf@qq.com>

[t1emu & t1rocketemu] fix vrf idx calculation

Signed-off-by: Clo91eaf <Clo91eaf@qq.com>
Signed-off-by: Clo91eaf <Clo91eaf@qq.com>
Signed-off-by: Clo91eaf <Clo91eaf@qq.com>
1. Add laneScale parameter.
2. Expand the data path in lane from elen to elen * laneScale.
3. Processing data units allows it to calculate more data in parallel or
   in multiple times.
1. Processing control signals bit of instruction tags.
2. Process the configuration of each slot accessing vfu.
3. Handled control signals when chainingSize is not a power of 2.
Signed-off-by: Avimitin <dev@avimit.in>
Signed-off-by: Avimitin <dev@avimit.in>
@sequencer sequencer merged commit 0f53401 into master Apr 22, 2025
@sequencer sequencer deleted the lane-data-width branch April 22, 2025 07:10
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5 participants