- used for communicating data between 2 asynchronous clock domains
- Closed-Loop sampling (implements an acknowledge protocol at CDC boundary)
- Accomodates the data crossing irrespective of frequecy/phase difference between the domains
- Suffers from greater latency compared to other methods
| Folder | Description |
|---|---|
| rtl/SystemVerilog | SV RTL implementation files |
| rtl/VHDL | VHDL RTL implementation files |
| cocotb_sim | Functional Verification with CoCoTB (Python-based) |
| pyuvm_sim | Functional Verification with pyUVM (Python impl. of UVM standard) |
| uvm_sim | Functional Verification with UVM (SV impl. of UVM standard) |
| verilator_sim | Functional Verification with Verilator (C++ based) |
This is the tree view of the strcture of the repo.
. ├── rtl │ ├── SystemVerilog │ │ └── SV files │ └── VHDL │ └── VHD files ├── cocotb_sim │ ├── Makefile │ └── python files ├── pyuvm_sim │ ├── Makefile │ └── python files ├── uvm_sim │ └── .zip file └── verilator_sim ├── Makefile └── verilator tb