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    230 repositories

    • nldiff

      Public
      Simple netlist comparison utility
      Python
      •
      Apache License 2.0
      •2•5•0•1•Updated Mar 6, 2025Mar 6, 2025

    • frigate_user_project

      Public
      Verilog
      •5•0•0•0•Updated Feb 28, 2025Feb 28, 2025

    • timing-scripts

      Public
      Python
      •5•0•3•0•Updated Feb 28, 2025Feb 28, 2025

    • IHP-Open-PDK

      Public
      130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design
      HTML
      •
      Apache License 2.0
      •81•1•1•0•Updated Feb 28, 2025Feb 28, 2025

    • sky130_ef_ip__simple_por

      Public
      Simple PoR based on an RC filter
      Shell
      •
      Apache License 2.0
      •3•0•0•0•Updated Feb 26, 2025Feb 26, 2025

    • sky130_ef_ip__adc3v_12bit

      Public
      12-bit ADC using other analog component repositories for the sample & hold, DAC, and comparator.
      Verilog
      •
      Apache License 2.0
      •5•0•0•0•Updated Feb 26, 2025Feb 26, 2025

    • sky130_ef_ip__rdac3v_8bit

      Public
      8-bit resistor ladder DAC with 3.3V output range
      MATLAB
      •
      Apache License 2.0
      •5•1•0•0•Updated Feb 26, 2025Feb 26, 2025

    • openlane-metrics

      Public
      Repository to store metric results for OpenLane 2.0.0+
      3•0•0•0•Updated Feb 26, 2025Feb 26, 2025

    • caravel

      Public
      Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
      magicyosyscaravelpicorv32openroadvexriscvopenramsky130
      Verilog
      •
      Apache License 2.0
      •80•319•96•5•Updated Feb 26, 2025Feb 26, 2025

    • openlane2

      Public
      The next generation of OpenLane, rewritten from scratch with a modular architecture
      flowasicedaverilogvlsipnrsiliconlvsflowssta
      Python
      •
      Apache License 2.0
      •57•276•88•9•Updated Feb 26, 2025Feb 26, 2025

    • openlane2-step-unit-tests

      Public
      Step-specific Unit Tests for OpenLane 2.0.0+
      Verilog
      •
      Apache License 2.0
      •4•0•0•1•Updated Feb 26, 2025Feb 26, 2025

    • EF_AES

      Public
      Verilog
      •3•0•1•1•Updated Feb 26, 2025Feb 26, 2025

    • EF_PSRAM_CTRL

      Public
      Verilog
      •
      Apache License 2.0
      •4•3•3•1•Updated Feb 26, 2025Feb 26, 2025

    • frigate-os

      Public
      Verilog
      •
      Apache License 2.0
      •8•4•0•0•Updated Feb 26, 2025Feb 26, 2025

    • frigate_analog

      Public
      The analog signal processing and timing frontend subsystems for the Frigate harness chip
      Verilog
      •
      Apache License 2.0
      •3•0•1•1•Updated Feb 26, 2025Feb 26, 2025

    • chipignite_discover

      Public
      HTML
      •
      Apache License 2.0
      •5•0•0•0•Updated Feb 26, 2025Feb 26, 2025

    • Caravel_on_FPGA

      Public
      Verilog
      •3•4•1•0•Updated Feb 25, 2025Feb 25, 2025

    • mpw_precheck

      Public
      Python
      •
      Apache License 2.0
      •29•37•40•7•Updated Feb 25, 2025Feb 25, 2025

    • caravel_user_project

      Public template
      https://caravel-user-project.readthedocs.io
      Verilog
      •
      Apache License 2.0
      •347•193•85•22•Updated Feb 25, 2025Feb 25, 2025

    • sky130_ef_ip__samplehold

      Public
      Analog 3.3V sample and hold circuit, with buffered output
      Tcl
      •
      Apache License 2.0
      •4•0•0•0•Updated Feb 25, 2025Feb 25, 2025

    • ipm

      Public
      Open-source IPs Package Manager (IPM)
      Python
      •
      Apache License 2.0
      •7•14•7•0•Updated Feb 24, 2025Feb 24, 2025

    • nix-eda

      Public
      Nix derivations for EDA tools
      nixedaelectronic-design-automationnix-flake
      Nix
      •
      Apache License 2.0
      •7•10•2•0•Updated Feb 24, 2025Feb 24, 2025

    • caravel_user_sram

      Public
      Verilog
      •
      Apache License 2.0
      •3•4•7•1•Updated Feb 24, 2025Feb 24, 2025

    • sky130_ef_ip__template

      Public template
      A template repository for analog designs to ensure consistency and interoperability between IP blocks.
      Apache License 2.0
      •3•0•0•0•Updated Feb 24, 2025Feb 24, 2025

    • EF_SRAM_1024x32

      Public
      Verilog
      •3•3•7•0•Updated Feb 23, 2025Feb 23, 2025

    • EF_SHA256

      Public
      Verilog
      •2•0•2•1•Updated Feb 23, 2025Feb 23, 2025

    • caravel_SI_testing

      Public
      C
      •4•2•3•5•Updated Feb 23, 2025Feb 23, 2025

    • openlane2-ci-designs

      Public
      Continuous Integration Designs for OpenLane 2.0.0 or higher
      Verilog
      •6•0•0•0•Updated Feb 23, 2025Feb 23, 2025

    • central_CI

      Public
      3•0•1•5•Updated Feb 22, 2025Feb 22, 2025

    • openframe_timer_example

      Public
      Example digital project for the Efabless Caravel "openframe" harness
      Verilog
      •
      Apache License 2.0
      •17•4•3•0•Updated Feb 21, 2025Feb 21, 2025